
Niveditha Nandakumar Kamath
Verification Engineer with a demonstrated history of working in the PCIe PIPE4.4.1,PIPE5.2,PIPE 6 interface and PCIe PL. Skilled... | San Jose, California, United States
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Niveditha Nandakumar Kamath’s Emails nk****@ca****.com
Niveditha Nandakumar Kamath’s Phone Numbers No phone number available.
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Niveditha Nandakumar Kamath’s Location San Jose, California, United States
Niveditha Nandakumar Kamath’s Expertise Verification Engineer with a demonstrated history of working in the PCIe PIPE4.4.1,PIPE5.2,PIPE 6 interface and PCIe PL. Skilled VerilogHDL, System Verilog, UVM, Microsoft Excel, Microsoft Word and C++. Strong engineering professional with a Bachelor’s Degree focused in Electronics and Communications Engineering from College of Engineering, Cherthala.
Niveditha Nandakumar Kamath’s Current Industry Cadence Design Systems
Niveditha
Nandakumar Kamath’s Prior Industry
Hardware Technology Group Of C Dac Pune
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Ibm
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Cadence Design Systems
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Work Experience

Cadence Design Systems
Design Engineer II
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Design Engineer
Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Intern
Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Biztalk Developer
Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Hardware Technology Group Of C Dac Pune
Interfacing GPS receiver to PIC microcontroller [Intern]
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)